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high voltage latch-up proof, quad spst switches adg5212/adg5213 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features latch-up proof 3 pf off source capacitance 5 pf off drain capacitance 0.07 pc charge injection low leakage: 0.2 na maximum at 85 o c 9 v to 22 v dual-supply operation 9 v to 40 v single-supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v ss to v dd analog signal range applications automatic test equipment data acquisition instrumentation avionics audio and video switching communication systems functional block diagrams in1 s1 d1 in2 s2 d2 in 3 s3 d3 in4 s4 d4 adg5212 switches shown for a logic 1 input. in2 s2 d2 in3 s3 d3 in1 s1 d1 in4 s4 d4 adg5213 09767-001 figure 1. general description the adg5212/adg5213 contain four independent single- pole/single-throw (spst) switches. the adg5212 switches turn on with logic 1. the adg5213 has two switches with digital control logic similar to that of the adg5212; however, the logic is inverted on the other two switches. each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. the adg5212 and adg5213 do not have a v l pin. the digital inputs are compatible with 3 v logic inputs over the full operating supply range. the ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. fast switching speed together with high signal bandwidth make the parts suitable for video signal switching. product highlights 1. trench isolation guards against latch-up. a dielectric trench separates the p and n channel transistors, thereby preventing latch-up even under severe overvoltage conditions. 2. ultralow capacitance and <1 pc charge injection. 3. dual-supply operation. for applications where the analog signal is bipolar, the adg5212/adg5213 can be operated from dual supplies of up to 22 v. 4. single-supply operation. for applications where the analog signal is unipolar, the adg5212/adg5213 can be operated from a single rail power supply of up to 40 v. 5. 3 v logic-compatible digital inputs. v inh = 2.0 v, v inl = 0.8 v. 6. no v l logic power supply required.
adg5212/adg5213 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply........................................................................ 5 36 v single supply........................................................................ 6 continuous current per channel, sx or dx..............................7 absolute maximum ratings ............................................................8 esd caution...................................................................................8 pin configurations and function descriptions ............................9 typical performance characteristics ........................................... 10 test circuits..................................................................................... 14 terminology .................................................................................... 16 trench isolation.............................................................................. 17 applications information .............................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 4/11revision 0: initial version
adg5212/adg5213 rev. 0 | page 3 of 20 specifications 15 v dual supply v dd = +15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v max on resistance, r on 160 typ v s = 10 v, i s = ?1 ma, see figure 24 200 250 280 max v dd = +13.5 v, v ss = ?13.5 v on-resistance match between channels, ?r on 2 typ v s = 10 v, i s = ?1 ma 8 9 10 max on-resistance flatness, r flat(on) 38 typ v s = 10 v, i s = ?1 ma 50 65 70 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.01 na typ v s = 10 v, v d = ? 10 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off) 0.01 na typ v s = 10 v, v d = ? 10 v, see figure 23 0.1 0.2 0.4 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 10 v, see figure 26 0.2 0.25 0.9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 175 ns typ r l = 300 , c l = 35 pf 210 255 280 ns max v s = 10 v, see figure 30 t off 140 ns typ r l = 300 , c l = 35 pf 170 195 215 ns max v s = 10 v, see figure 30 break-before-make time delay, t d (adg5213 only) 40 ns typ r l = 300 , c l = 35 pf 20 ns min v s1 = v s2 = 10 v, see figure 29 charge injection, q inj 0.07 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 31 off isolation ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 25 channel-to-channel crosstalk ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 27 ?3 db bandwidth 435 mhz typ r l = 50 , c l = 5 pf, see figure 28 insertion loss ?6.8 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 c s (off) 3 pf typ v s = 0 v, f = 1 mhz c d (off) 5 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 8 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test.
adg5212/adg5213 rev. 0 | page 4 of 20 20 v dual supply v dd = +20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v max on resistance, r on 140 typ v s = 15 v, i s = ?1 ma, see figure 24 160 200 230 max v dd = +18 v, v ss = ?18 v on-resistance match between channels, ?r on 1.5 typ v s = 15 v, i s = ?1 ma 8 9 10 max on-resistance flatness, r flat(on) 33 typ v s = 15 v, i s = ?1 ma 45 55 60 max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0.01 na typ v s = 15 v, v d = ? 15 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.01 na typ v s = 15 v, v d = ? 15 v, see figure 23 0.1 0.2 0.4 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 15 v, see figure 26 0.2 0.25 0.9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 155 ns typ r l = 300 , c l = 35 pf 195 235 255 ns max v s = 10 v, see figure 30 t off 145 ns typ r l = 300 , c l = 35 pf 165 185 210 ns max v s = 10 v, see figure 30 break-before-make time delay, t d (adg5213 only) 35 ns typ r l = 300 , c l = 35 pf 20 ns min v s1 = v s2 = 10 v, see figure 29 charge injection, q inj ?0.5 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 31 off isolation ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 25 channel-to-channel crosstalk ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 27 ?3 db bandwidth 460 mhz typ r l = 50 , c l = 5 pf, see figure 28 insertion loss ?6 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 c s (off ) 2.8 pf typ v s = 0 v, f = 1 mhz c d (off ) 4.8 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 8 pf typ v s = 0 v, f = 1 mhz
adg5212/adg5213 rev. 0 | page 5 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v max on resistance, r on 350 typ v s = 0 v to 10 v, i s = ?1 ma, see figure 24 500 610 700 max v dd = 10.8 v, v ss = 0 v on-resistance match between channels, ?r on 4 typ v s = 0 v to 10 v, i s = ?1 ma 20 21 22 max on-resistance flatness, r flat(on) 160 typ v s = 0 v to 10 v, i s = ?1 ma 280 335 370 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.01 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off) 0.01 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 23 0.1 0.2 0.4 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 1 v/10 v, see figure 26 0.2 0.25 0.9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 235 ns typ r l = 300 , c l = 35 pf 290 360 410 ns max v s = 8 v, see figure 30 t off 165 ns typ r l = 300 , c l = 35 pf 205 235 260 ns max v s = 8 v, see figure 30 break-before-make time delay, t d (adg5213 only) 85 ns typ r l = 300 , c l = 35 pf 50 ns min v s1 = v s2 = 8 v, see figure 29 charge injection, q inj ?0.5 pc typ v s = 6 v, r s = 0 , c l = 1 nf, see figure 31 off isolation ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 25 channel-to-channel crosstalk ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 27 ?3 db bandwidth 340 mhz typ r l = 50 , c l = 5 pf, see figure 28
adg5212/adg5213 rev. 0 | page 6 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments insertion loss ?11 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 c s (off) 3.5 pf typ v s = 6 v, f = 1 mhz c d (off) 5.5 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 9 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 65 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v max on resistance, r on 150 typ v s = 0 v to 30 v, i s = ?1 ma, see figure 24 170 215 245 max v dd = 32.4 v, v ss = 0 v on-resistance match between channels, ?r on 1.6 typ v s = 0 v to 30 v, i s = ?1 ma 8 9 10 max on-resistance flatness, r flat(on) 35 typ v s = 0 v to 30 v, i s = ?1 ma 50 60 65 max leakage currents v dd =39.6 v, v ss = 0 v source off leakage, i s (off) 0.01 na typ v s = 1 v/30 v, v d = 30 v/1 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off) 0.01 na typ v s = 1 v/30 v, v d = 30 v/1 v, see figure 23 0.1 0.2 0.4 na max channel on leakage, i d (on), i s (on) 0.02 na typ v s = v d = 1 v/30 v, see figure 26 0.2 0.25 0.9 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on 190 ns typ r l = 300 , c l = 35 pf 230 255 265 ns max v s = 18 v, see figure 30 t off 175 ns typ r l = 300 , c l = 35 pf 215 230 245 ns max v s = 18 v, see figure 30 break-before-make time delay, t d (adg5213 only) 45 ns typ r l = 300 , c l = 35 pf 25 ns min v s1 = v s2 = 18 v, see figure 29 charge injection, q inj ?0.5 pc typ v s = 18 v, r s = 0 , c l = 1 nf, see figure 31 off isolation ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 25 channel-to-channel crosstalk ?105 db typ r l = 50 , c l = 5 pf, f = 1 mhz, figure 27
adg5212/adg5213 rev. 0 | page 7 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments ?3 db bandwidth 410 mhz typ r l = 50 , c l = 5 pf, see figure 28 insertion loss ?6.8 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 c s (off) 3 pf typ v s = 18 v, f = 1 mhz c d (off) 5 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 8 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. continuous current per channel, sx or dx table 5. parameter 25c 85c 125c unit continuous current, sx or dx v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 18 10 5 ma maximum lfcsp ( ja = 30.4c/w) 32 15 6 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 29 16 8 ma maximum lfcsp ( ja = 30.4c/w) 50 22 9 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 18 12 7 ma maximum lfcsp ( ja = 30.4c/w) 32 17 8 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 34 18 8 ma maximum lfcsp ( ja = 30.4c/w) 59 24 9 ma maximum
adg5212/adg5213 rev. 0 | page 8 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or dx pin 60 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, sx or dx 2 data + 15% temperature operating range ?40c to +125c storage range ?65c to +150c junction 150c thermal impedance, ja 16-lead tssop (4-layer board) 112.6c/w 16-lead lfcsp (4-layer board) 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c 1 overvoltages at the inx, sx, and dx pins are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution
adg5212/adg5213 rev. 0 | page 9 of 20 pin configurations and function descriptions in1 1 d1 2 s1 3 v ss 4 in2 16 d2 15 s2 14 v dd 13 gnd 5 nc 12 s4 6 s3 11 d4 7 d3 10 in4 8 in3 9 nc = no connect adg5212/ adg5213 top view (not to scale) 09767-002 figure 2. tssop pin configuration notes 1. exposed pad tied to substrate, v ss . 2. nc = no connect. 1 s1 2 v ss 3 gnd 4 s4 11 v dd 12 s2 10 nc 9s3 5 d 4 6 i n 4 7 i n 3 8 d 3 1 5 i n 1 1 6 d 1 1 4 i n 2 1 3 d 2 top view (not to scale) adg5212/ adg5213 09767-003 figure 3. lfcsp pin configuration table 7. pin function descriptions pin no. tssop lfcsp neonic description 1 15 in1 logic control input. 2 16 d1 drain terminal. this pin can be an input or an output. 3 1 s1 source terminal. this pin can be an input or an output. 4 2 v ss most negative power supply potential. 5 3 gnd ground (0 v) reference. 6 4 s4 source terminal. this pin can be an input or an output. 7 5 d4 drain terminal. this pin can be an input or an output. 8 6 in4 logic control input. 9 7 in3 logic control input. 10 8 d3 drain terminal. this pin can be an input or an output. 11 9 s3 source terminal. this pin can be an input or an output. 12 10 nc no connect. these pins are open. 13 11 v dd most positive power supply potential. 14 12 s2 source terminal. this pin can be an input or an output. 15 13 d2 drain terminal. this pin can be an input or an output. 16 14 in2 logic control input. n/a 1 ep exposed pad exposed pad. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capabili ty, it is recommended that the pad be soldered to the substrate, v ss . 1 n/a means not applicable. table 8. adg5212 truth table adg5212 in switch condition 1 on 0 off table 9. adg5213 truth table adg5213 in s1, s4 s2, s3 0 off on 1 on off
adg5212/adg5213 rev. 0 | page 10 of 20 typical performance characteristics 160 0 20 40 60 80 100 120 140 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09767-104 figure 4. r on as a function of v s , v d (dual supply) 250 200 150 100 50 0 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +13.2v v ss = ?13.2v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 09767-105 figure 5. r on as a function of v s , v d (dual supply) 500 450 400 350 300 250 200 150 100 50 0 01 4 12 10 8642 on resistance ( ? ) v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10.8v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 09767-106 figure 6. r on as a function of v s , v d (single supply) 160 140 120 100 80 60 40 20 0 04 353025201510 5 on resistance ( ? ) v s , v d (v) 0 t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v 09767-107 figure 7. r on as a function of v s , v d (single supply) 250 200 150 100 50 0 ?15 ?10 ?5 0 5 10 15 on resistance ( ? ) v s, v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 09767-108 figure 8. r on as a function of v s , v d for different temperatures, 15 v dual supply 200 160 120 80 40 180 140 100 60 20 0 ?20 ?15 ?10 ?5 0 5 10 20 15 on resistance ( ? ) v s, v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09767-109 figure 9. r on as a function of v s , v d for different temperatures, 20 v dual supply
adg5212/adg5213 rev. 0 | page 11 of 20 500 400 300 200 100 450 340 250 150 50 0 024681012 on resistance ( ? ) v s, v d (v) v dd = 12v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09767-110 figure 10. r on as a function of v s , v d for different temperatures, 12 v single supply 250 200 100 150 50 0 03 5 30 25 20 15 10 5 on resistance ( ? ) v s, v d (v) v dd = 36v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09767-111 figure 11. r on as a function of v s ,v d for different temperatures, 36 v single supply 40 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 255075100125 leakage current (pa) temperature (c) v dd = +15v v ss = ?15v v bias = +10v/?10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09767-112 figure 12. leakage currents vs. temperature, 15 v dual supply 100 ?200 ?150 ?100 ?50 0 50 0 255075100125 leakage current (pa) temperature (c) v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09767-113 figure 13. leakage currents vs. temperature, 20 v dual supply 40 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 255075100125 leakage current (pa) temperature (c) v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09767-114 figure 14. leakage currents vs. temperature, 12 v single supply 50 ?250 ?200 ?150 ?100 ?50 0 0 255075100125 leakage current (pa) temperature (c) v dd = 36v v ss = 0v v bias = 1v/30v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09767-115 figure 15. leakage currents vs. temperature, 36 v single supply
adg5212/adg5213 rev. 0 | page 12 of 20 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10k 100k 1g 100m 10m 1m off isolation (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 09767-120 figure 16. off isolation vs. frequency, 15 v dual supply 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10k 100k 1g 100m 10m 1m crosstalk (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 09767-121 figure 17. crosstalk vs. frequency, 15 v dual supply 6 ?2 ?1 0 1 2 3 4 5 ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) t a = 25c source to drain v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09767-122 figure 18. charge injection vs. source voltage 0 ?120 ?100 ?80 ?60 ?40 ?20 1k 10k 100k 10m 1m acpsrr (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v no decoupling capacitors decoupling capacitors 09767-123 figure 19. acpsrr vs. frequency, 15 v dual supply 0 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 100k 1g 100m 10m 1m attenuation (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 09767-125 figure 20. bandwidth ?15 ?10 ?5 0 5 10 15 v s (v) 0 12 10 8 6 4 2 capacitance (pf) t a = 25c v dd = +15v v ss = ?15v source/drain on drain off source off 09767-127 figure 21. capacitance
adg5212/adg5213 rev. 0 | page 13 of 20 0 ?120 ?100 ?80 ?60 ?40 ?20 ?40 ?20 120 10080604020 0 time (ns) temperature (c) t a = 25c v dd = +15v v ss = ?15v t on (+12v) t on (+36v) t off (+12v) t off (+36v) t on (15v) t on (20v) t off (20v) t off (15v) 09767-126 figure 22. t on , t off times vs. temperature
adg5212/adg5213 rev. 0 | page 14 of 20 test circuits sd v s a a v d i s (off) i d (off) 09767-015 figure 23. off leakage sd v s v1 i ds r on = v 1 /i ds 09767-014 figure 24. on resistance v out 50? network analyzer r l 50 ? inx v in sx dx 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 09767-020 figure 25. off isolation v d sd v s a i d (on) 09767-016 figure 26. on leakage channel-to-channel crosstalk = 20 log v out gnd s1 dx s2 v out network analyzer r l 50? r l 50 ? v s v s v dd v ss 0.1f v dd 0.1f v ss 09767-021 figure 27. channel-to-channel crosstalk v out 50? network analyzer r l 50 ? inx v in sx dx off isolation = 20 log v s v out with switch v out without switch v dd v ss 0.1f v dd 0.1f v ss gnd 09767-028 figure 28. bandwidth
adg5212/adg5213 rev. 0 | page 15 of 20 v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300 ? c l 35pf v out2 v out1 v dd v ss 0.1f v dd 0.1f v ss v in v out1 v out2 adg5213 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300 ? c l 35pf 09767-017 figure 29. break-before-make time delay, t d v s inx sx dx gnd r l 300 ? c l 35pf v out v dd v ss 0.1f v dd 0.1f v ss adg5212 v in v out t on t off 50% 50% 90% 90% 09767-018 figure 30. switching times in v out adg5212 v in v out off ? v out on q inj = c l ? v out sd v dd v ss v dd v ss v s r s gnd c l 1nf 09767-019 figure 31. charge injection
adg5212/adg5213 rev. 0 | page 16 of 20 terminology i dd i dd represents the positive supply current. i ss i ss represents the negative supply current. v d , v s v d and v s represent the analog voltage on terminal dx and terminal sx, respectively. r on r on represents the ohmic resistance between terminal dx and ter mina l sx . r on r on represents the difference between the r on of any two channels. r flat(on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by r flat(on) . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in is the digital input capacitance. t on t on represents the delay between applying the digital control input and the output switching on (see figure 30 ). t off t off represents the delay between applying the digital control input and the output switching off (see figure 30 ). t d t d represents the off time measured between the 80% point of both switches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off switch. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is the frequency at which the output is attenuated by 3 db. on response on response is the frequency response of the on switch. insertion loss insertion loss is the loss due to the on resistance of the switch. ac power supply rejection ratio (acpsrr) ac power supply rejection ratio (acpsrr) is the ratio of the amplitude of signal on the output to the amplitude of the modula- tion. this is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
adg5212/adg5213 rev. 0 | page 17 of 20 trench isolation in the adg5212 and adg5213, an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse-biased under normal operation. however, during overvoltage conditions, this diode can become forward-biased. a silicon controlled rectifier (scr) type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. with trench isolation, this diode is removed and the result is a latch- up proof switch. nmos pmos pwell nwell buried oxide layer handle wafer trench 09767-022 figure 32. trench isolation
adg5212/adg5213 rev. 0 | page 18 of 20 applications information the adg52xx family of switches and multiplexers provides a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. the adg5212/adg5213 high voltage switches allow single-supply operation from 9 v to 40 v and dual-supply operation from 9 v to 22 v.
adg5212/adg5213 rev. 0 | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 33. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c figure 34. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very very thin quad (cp-16-17) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg5212bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5212bruz-rl7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5212bcpz-rl7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-17 adg5213bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5213bruz-rl7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 ADG5213BCPZ-RL7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-17 1 z = rohs compliant part.
adg5212/adg5213 rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09767-0-4/11(0)

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